The invention disclosed herein relates generally to a method and apparatus for fabricating semiconductor integrated circuit devices. More particularly, the present invention relates to method and apparatus for eliminating interconnect extrusions in vias.
As integrated circuits become increasingly smaller and more complex, multiple levels of metallization are used to interconnect circuits on devices. Multilevel metallization is used to conserve chip area while minimizing interconnection resistance. Aluminum and aluminum alloys are generally the predominant interconnect material in metallization systems, but aluminum from the underlying interconnect metallization extrudes into vias during conventional ionized metal plasma (xe2x80x9cIMPxe2x80x9d) processing of the adhesion and barrier layers used for the formation of tungsten plugs in vias.
During metallization, interconnects are formed over metal contacts to provide electrically conductive paths. A dielectric layer is deposited by conventional processes on the metal interconnects. This dielectric layer is etched to form a window or via to expose a portion of the interconnect where the electrical interconnection will be made. The via is then filled with electrically conductive material. To promote formation and to prohibit harmful diffusion, adhesion and barrier layers are used to line the inside of the via before filling the via with an electrically conductive plug material, such as tungsten, copper or copper alloys. Vias are used to electrically connect the metal interconnects on subsequent interconnect levels.
With reference to FIG. 1, a schematic partial sectional view of an example of the first two layers of a conventional submicron, complimentary metal oxide semiconductor (CMOS) device is illustrated. A first dielectric layer 126 is deposited using conventional processes over the gates 120 and the substrate 110. The device level 130 consists of the layers of the semiconductor 100 up to and including the first dielectric layer 126.
A plurality of contacts 124 over the doped source and drain regions 118 may be formed by conventional processes. These contacts 124 are typically made from interconnect materials, such as aluminum, aluminum alloys, tungsten, or other suitable electrically conducting materials known to one skilled in the art. A plurality of interconnects 140 are patterned by photolithography and formed using plasma processing over the metal contacts 124 to form electrically conductive paths. For example, the contact windows 124 may be filled with tungsten deposited using techniques well known in the prior art. The structures may then be planarized using chemical-mechanical polishing or etch-back techniques to form tungsten plugs. A layer of conductive metals is then depositied to form the runners or interconnects 140. The interconnects are made of electrically conductive materials, such as aluminum, aluminum-copper alloys, aluminum-silicon-copper alloys and other aluminum alloys known to one skilled in the art. These aluminum-alloys may be deposited with refractory material under-layers such as titanium, titanium nitride or combinations of both. These multilevel metal stacks may be deposited using sputter deposition techniques, patterned and etched using methods well known in the prior art. A second dielectric layer 142 is deposited by conventional processes on the runners or interconnects 140. Substrates 100 typically may include several interconnect layers 150, wherein a plurality of vias 144 are used to electrically connect the metal interconnects or runners 140 on subsequent interconnect levels.
In FIG. 2, a schematic sectional view of a conventional via structure is illustrated. The via 144 is lined with a coating 155 by IMP techniques. Typically for better chip reliability, the coating will comprise two layers, an adhesion layer 160 which is coated with a barrier layer 165. However, one skilled in the art will recognize that the coating 155 may consist of only one, or may consist of more than two layers. The composition of the adhesion layer 160/barrier layer 165 is generally Ti/TiN, Ta/TaN, W/WN or other materials known to one skilled in the art. A plug 170 is then formed over the barrier layer 165 to fill in the via 144. The plug 170 is comprised of tungsten or other materials known to one skilled in the art. The plug is deposited using conventional methods known to one skilled in the art, such as chemical vapor deposition (xe2x80x9cCVDxe2x80x9d) techniques.
For devices that have large current requirements, designers often route the signals through higher metal interconnect levels, such as the final two levels of metal interconnects 168 shown in FIG. 3. To capitalize on the lower resistivity of copper compared to aluminum, designers often use copper and copper alloys and other materials known to those skilled in the art as the interconnect materials for these high level interconnects 166. The interconnects 166 are surrounded by dielectric layers 162, 163, and 164. The vias 167 connect the interconnects 166 to form electrically conductive paths.
The most common methods used today for depositing copper and copper alloys is electroplating. To deposit copper and copper alloys using an electroplating technique requires the deposition of a conductive seeding layer prior to deposition of the copper or copper alloy plug. Referring to FIG. 4, a schematic sectional view of a conventional via structure for higher level metal interconnects 168 is illustrated. The via 167 is lined with a coating 177. The deposition of copper also requires the prior deposition of an adhesion and barrier layer stack where copper is used in the damascene or dual damascene structures fabricated in the dielectric. Typically for better chip reliability, the coating will comprise three layers, an adhesion layer 172 which is coated with a barrier layer 174 which is then coated with a sceding layer 176. However, one skilled in the art will recognize that the coating 177 may consist of only one, or may consist of more than two layers. Since copper migrates very rapidly through dielectrics, it is contained by depositing barrier layer(s) 174 prior to deposition of the seeding layer 176. Those skilled in the art will recognize that a preferred method of depositing the adhesion layer 172 and barrier layer 174 stack is IMP. One skilled in the art will recognize that the adhesion and barrier layer(s) may be comprised of one or more layers of tantalum/tantalum nitride/tantalum silicon nitride, tungsten/tungsten nitride/tungsten silicon nitride, titanium/titanium nitride or combinations thereof. Copper and copper alloys are the preferred choice for the seeding layer 176. Those skilled in the art will also recognize that a preferred method of depositing the seeding layer 176 is IMP.
During the deposition of refractory materials to form the coating 155, 177 such as the Ti/TiN using IMP techniques, the wafer tends to be heated due to highly localized heating effects. This heat is derived from the plasma, the RF coil used to generate the plasma, and the latent heat of condensation from ion bombardment from the materials being deposited on the wafer. The temperature during IMP processing gets hot enough to result in the aluminum from the underlying interconnect metallization extruding into the vias.
The extrusion of the aluminum from the underlying metallization layer also occurs during IMP deposition of the adhesion/barrier/seeding layers in devices where the higher interconnect levels are copper and the lower level interconnects are aluminum. For example, in a device having six metal interconnect levels where the first four interconnect levels are comprised of aluminum and the last two levels are comprised of copper, when the fifth layer of the copper damascene or dual damascene structure is deposited, the aluminum from the fourth interconnect level extrudes through the via from the fourth level to the fifth interconnect level.
It is an object of the present invention to provide a method and system for eliminating extrusions of the interconnect metallization into vias during IMP processing.
It is another object of this invention to decrease reliability failures and to decrease yield loss due to interconnect extrusions into vias.
It is yet another object of the present invention to provide a low cost method and system that can be easily implemented in standard processing equipment to eliminate interconnect extrusions into vias during IMP processing.
The above and other objects are achieved by controlling the interconnect temperature during IMP processing. The extrusions of interconnect metallization occur while wafers are subject to elevated temperatures that cause the internal stresses in the interconnect Metallization to transit from a substantially tensile mode to a substantially compressive mode. Once the interconnect metallization is under compression, it relieves stress by extruding into the via etched into the inter-level dielectric on top of the interconnect metallization. By controlling the interconnect temperature to be below the temperature at which the interconnect stress transits from a tensile to a compressive mode, interconnect extrusions in vias are eliminated. By eliminating these extrusions, wafer reliability is improved and processing yield loss due to a high number of defects is decreased.
In one embodiment, the interconnect temperature is controlled by using an actively cooled pedestal in combination with a low temperature IMP deposition process, thereby preventing aluminum extrusions from poisoning the vias.
In another embodiment, in addition to active pedestal cooling and low IMP processing temperatures, the IMP processing time is decreased to limit heating of the interconnect.